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Micrel, Inc.
3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD
SY88843V
SY88843V
FEATURES
s Multi-rate up to 3.2Gbps operation s Wide gain-bandwidth product * 38dB differential gain * 2GHz 3dB bandwidth s Low noise 50 CML data outputs * 800mVPP output swing * 60ps edge rates * 5psRMS typ. random jitter * 15psPP typ. deterministic jitter s Chatter-free, Signal-Detect (SD) output * 4.6dB electrical hysteresis * OC-TTL output with internal 4.75k pull-up resistor s Programmable SD sensitivity using single external resistor s Internal 50 data input termination s TTL EN input allows feedback from SD s Wide operating range * Single 3.3V 10% or 5V 10% power supply * -40C to +85C industrial temperature range s Available in tiny 10-pin EPAD-MSOP and 16-pin MLFTM packages
DESCRIPTION
The SY88843V low-power limiting post amplifier is designed for use in fiber-optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88843V quantizes these signals and outputs typically 800mVPP voltage-limited waveforms. The SY88843V operates from a single +3.3V 10% or +5V 10% power supply, over an industrial temperature range of -40C to +85C. With its wide bandwidth and high gain, signals with data rates up to 3.2Gbps and as small as 10mVp-p can be amplified to drive devices with CML inputs or AC-coupled PECL inputs. The SY88843V incorporates a signal detect (SD), opencollector TTL output with internal 4.75k pull-up resistor. A programmable, loss-of-signal level set pin (SDLVL) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold set by SDLVL and de-asserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a loss of signal condition. EN asserts the true output signal without removing the input signal. Typically 4.6dB SD hysteresis is provided to prevent chattering. Please see Micrel's website at www.micrel.com for a complete selection of optical module ICs. The following table summarizes the differences between devices in Micrel's latest family of Limiting Amplifiers. All support documentation can be found on Micrel's web site at www.micrel.com.
Part Number SY88773V SY88823V SY88843V SY88973V Integrated 50 Input Termination No No Yes Yes LOS or SD LOS SD SD LOS Active LOW or HIGH Enable LOW HIGH HIGH LOW
APPLICATIONS
s 1.25Gbps and 2.5Gbps Gigabit Ethernet s 1.062Gbps and 2.125Gbps Fibre Channel s 155Mbps, 622Mbps, 1.25Gbps, and 2.5Gbps SONET/ SDH s Gigabit interface converter (GBIC) s Small form factor (SFF) and small form factor pluggable (SFP) transceivers s Parallel 10G Ethernet s High-gain line driver and line receiver
Table 1. Limiting Amplifiers Selection Guide
TYPICAL PERFORMANCE
3.3V, 25C, 10mVpp Input @3.2Gbps 231-1 PRBS, RLOAD = 50 to VCC
Output Swing (75mV/div.)
Micro LeadFrame and MLF are trademarks of Amkor Technology
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TIME (50ps/div.)
Rev.: C Amendment: /0
1
Issue Date: November 2005
Micrel, Inc.
SY88843V
FUNCTIONAL BLOCK DIAGRAM
VCC DIN 50 /DIN REF REF Generator
Level Detect 2.8k TTL Buffer Limiting Amplifer CML Buffer
DOUT
/DOUT VCC
25k
EN
VCC
4.75k OC-TTL Buffer
SD
SDLVL
GND
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Micrel, Inc.
SY88843V
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
SDLVL VCC VCC
Part Number SY88843VKI
12 11 10 9
Package Type K10-2 K10-2 MLF-16 MLF-16 K10-2 K10-2 MLF-16 MLF-16
Operating Range Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
Package Marking 843V 843V 843V 843V 843V with Pb-Free bar-line indicator 843V with Pb-Free bar-line indicator 843V with Pb-Free bar-line indicator 843V with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Sn-Pb Sn-Pb Pb-Free Matte-Sn Pb-Free Matte-Sn Pb-Free NiPdAu Pb-Free NiPdAu
16
EN
15
14
13
DIN GND GND /DIN
1 2 3 4 5 6 7 8
/DOUT GND GND /DOUT
SY88843VKITR(2) SY88843VMI SY88843VMITR(2) SY88843VEY(3) SY88843VEYTR(2, 3) SY88843VMG(3) SY88843VMGTR(2, 3)
VCC
REF
16-Pin MLFTM (MLF-16)
EN 1 DIN 2 /DIN 3 REF 4 SDLVL 5 10 VCC 9 DOUT 8 /DOUT 7 SD 6 GND
VCC
SD
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
10-Pin EPAD-MSOP (K10-2)
PIN DESCRIPTION
Pin Number (MSOP) 1 Pin Number (MLFTM) 15 Pin Name EN Type TTL Input: Default is high. Differential Data Input Pin Function Enable: De-asserts true data output when low. Incorporates 25k pull-up to VCC. Differential data input. Each pin internally terminates to REF through 50. Reference Voltage: Bypass with 0.01F low ESR capacitor from REF to VCC to stabilize SDLVL and REF. Input: Default is maximum sensitivity. Ground Open Collector TTL Output with internal 4.75k pull-up resistor Differential CML Output Power Supply Signal Detect Level Set: A resistor from this pin to VCC sets the threshold for the data input amplitude at which the SD output will be asserted. Device ground. Exposed pad must be soldered (or equivalent) to the same potential as the ground pins. Signal Detect: Asserts high when the data input amplitude rises above the threshold set by SDLVL.
2, 3 4 5
1, 4 6 14
DIN, /DIN REF SDLVL
6 Exposed Pad 7
2, 3, 10, 11 Exposed Pad 7
GND SD
8, 9 10
9, 12 5, 8, 13, 16
DOUT, /DOUT VCC
Differential data output. Positive power supply. Bypass with 0.1F0.01F low ESR capacitors. 0.01F capacitors should be as close as possible to VCC pins.
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SY88843V
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ....................................... 0V to +7.0V EN, SDLVL Voltage ................................................0 to VCC REF Current ............................................................... 1mA SD Current ................................................................. 5mA DOUT, /DOUT Current ............................................. 25mA DIN, /DIN Current ..................................................... 10mA Storage Temperature (TS) ....................... -65C to +150C Lead Temperature (Soldering, 20 sec.) .................... 260C
Operating Ratings(2)
Supply Voltage (VCC) .............................. +3.0V to +3.6V or ............................................................ +4.5V to +5.5V Ambient Temperature (TA) ......................... -40C to +85C Junction Temperature (TJ) ....................... -40C to +120C Package Thermal Resistance(3) MLFTM JA (Still-Air) ..................................................... 61C/W JB ................................................................................... 38C/W EPAD-MSOP JA (Still-Air) ..................................................... 38C/W JB ................................................................................... 22C/W
DC ELECTRICAL CHARACTERISTICS
VCC = 3.0V to 3.6V or 4.5V to 5.5V, TA = -40C to +85C; typical values at VCC = 3.3V, TA = 25C Symbol ICC Parameter Power Supply Current Power Supply Current VREF SDLVL VOH VOL VOFFSET ZO ZI REF Voltage SDLVL Voltage Range DOUT, /DOUT HIGH Voltage DOUT, /DOUT LOW Voltage Differential Output Offset Single-Ended Output Impedance Single-Ended Input Impedance Note 6 3.3V, Note 6 5V, Note 6 Note 6 40 40 50 50 VREF VCC-0.020 VCC-0.005 Condition 3.3V, Note 4 5V, Note 4 3.3V, Note 5 5V, Note 5 Min Typ 28 30 45 47 VCC-1.3 VCC VCC Max 42 45 62 65 Units mA mA mA mA V V V V V mV
VCC-0.475 VCC-0.400 VCC-0.350 VCC-0.510 VCC-0.400 VCC-0.350 80 60 60
TTL DC ELECTRICAL CHARACTERISTICS
VCC = 3.0V to 3.6V or 4.5V to 5.5V, TA = -40C to +85C Symbol VOH VOL VIH VIL IIH IIL Parameter SD Output HIGH Level SD Output LOW Level EN Input HIGH Voltage EN Input LOW Voltage EN Input HIGH Current EN Input LOW Current VIN = 2.7V VIN = VCC VIN = 0.5V -0.3 Condition Sourcing 100A Sinking 2mA 2.0 0.8 20 100 Min 2.4 Typ Max VCC 0.5 Units V V V V A A mA
Notes: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Thermal performance assumes the use of 4-layer PCB. Exposed pad must be soldered (or equivalent) to the device's most negative potential on the PCB. 4. Excludes current of CML output stage. See "Detailed Description." 5. Total device current with no output load. 6. Output levels are based on a 50 to VCC load impedance. If the load impedance is different, the output level will be changed. Amplifier is in limiting mode. M9999-110905 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
SY88843V
AC ELECTRICAL CHARACTERISTICS
VCC = 3.0V to 3.6V or 4.5V to 5.5V, TA = -40C to +85C, RLOAD = 50 to VCC; typical values at VCC = 3.3V, TA = 25C. Symbol PSRR tr,tf tJITTER VID VOD HYS tOFF tON VSR B-3dB AV(Diff) S21
Notes: 7. Amplifier in limiting mode. Input is a 200MHz square wave, tr < 300ps. 8. Deterministic jitter measured using 2.488Gbps K28.5 pattern, VID = 10mVpp. Random jitter measured using 2.488Gbps K28.7 pattern, VID = 10mVpp. 9. Electrical signal. 10. This is the detectable range of input amplitudes that can de-assert SD. The input amplitude to assert SD is 2-8dB higher than the de-assert amplitude. See "Typical Operating Characteristics" for graphs showing how to choose a particular VSDLVL or RSDLVL for a particular SD de-assert, and its associated assert, amplitude. If increased SD sensitivity and hysteresis are required, an application note entitled "Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers" is available at http://www.micrel.com/product-info/app_hints+notes.shtml.
Parameter Power Supply Rejection Ratio Output Rise/Fall Time (20% to 80%) Deterministic Random Differential Input Voltage Swing Differential Output Voltage Swing SD Hysteresis SD Release Time SD Assert Time SD Sensitivity Range -3dB Bandwidth Differential Voltage Gain Single-Ended Small-Signal Gain
Condition
Min
Typ 35
Max
Units dB
Note 7 Note 8 10 3.3V, Note 7 5V, Note 7 Note 9 700 700 2
60 15 5
120
ps psPP psRMS
1800 800 800 4.6 0.1 0.2 950 1020 8 0.5 0.5 35 2.0
mVPP mVPP mVPP dB s s mVPP GHz dB dB
Note 10
10
32 26
38 32
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Micrel, Inc.
SY88843V
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, TA = 25C, RLOAD = 50 to VCC, unless otherwise stated.
10mVpp Input @3.2Gbps 231-1 PRBS
1.8Vpp Input @3.2Gbps 231-1 PRBS
Output Swing (75mV/div.)
TIME (50ps/div.)
Output Swing (75mV/div.)
TIME (50ps/div.)
100
VID to Assert/De-assert SD vs. VSDLVL
VID to Assert/De-assert SD vs. RSDLVL 100 40 35 30
Single-Ended Small-Signal Gain vs. Frequency
VID (mVpp)
VID (mVpp)
10
10
S21 (dB) 1 10 RSDLVL(k) 100 Differential Output Voltage Swing vs. Temperature (Amplifier in Limiting Mode) VOD (mVpp) -15 10 35 60 TEMPERATURE (C) 85
25 20 15 10 5
1
0
0.2
0.4 0.6 0.8 1.0 VCC - VSDLVL (V)
1.2
1 0.1
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 FREQUENCY (GHz)
60 55 CURRENT (mA) 50 45 40 35 30 25 -40
Power Supply Current vs. Temperature
900 880 860 VOD (mVpp) 840 820 800 780 760 740 720 700 -40
Differential Output Voltage Swing vs. Differential Input Voltage Swing 900 800 700 600 500 400 300 200 100 0 0 5 10 15 20 25 30 35 40 45 50 VID (mVpp)
-15 10 35 60 TEMPERATURE (C)
85
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SY88843V
DETAILED DESCRIPTION
The SY88843V low-power, limiting post amplifier operates from a single +3.3V 10% or +5V 10% power supply, over an industrial temperature range of -40C to +85C. Signals with data rates up to 3.2Gbps and as small as 10mVPP can be amplified. Figure 1 shows the allowed input voltage swing. The SY88843V generates an SD output, providing feedback to EN for output stability. SDLVL sets the sensitivity of the input amplitude detection. Input Amplifier/Buffer The SY88843V's inputs are internally terminated with 50 to REF. Unless unaffected by this internal termination scheme, upstream devices need to be AC-coupled to the SY88843V's inputs. Figure 2 shows a simplified schematic of the input structure. The high sensitivity of the input amplifier detects and amplifies as small as 10mVPP. The input amplifier allows input signals as large as 1800mVPP. Input signals are linearly amplified with a typically 38dB differential voltage gain. Since it is a limiting amplifier, the SY88843V outputs typically 800mVPP voltage-limited waveforms for input signals that are greater than 10mV PP . Applications requiring the SY88843V to operate with high gain should have the upstream TIA placed as close as possible to the SY88843V's input pins to ensure the device's best performance of the device. Output Buffer The SY88843V's CML output buffer is designed to drive 50 lines. The output buffer requires appropriate termination for proper operation. An external 50 resistor to VCC or equivalent for each output pin provides buffer termination. Figure 3 shows a simplified schematic of the output structure and includes an appropriate termination method. Of course, driving a downstream device with a CML input that is internally terminated with 50 to VCC eliminates the need for external termination. As noted in the previous section, the amplifier outputs, typically 800mVPP, waveforms across 25 total loads. The output buffer, thus, switches typically 16mA tail-current. Figure 4 shows the power supply current measurement which excludes the 16mA tail-current. Signal Detect The SY88843V incorporates a chatter-free, SD opencollector TTL output with internal 4.75k pull-up resistor as shown in Figure 5. SD is used to determine that the input amplitude large enough to be considered a valid input. SD asserts high if the input amplitude rises above the threshold set by SDLVL and de-asserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a loss-of-signal condition. EN de-asserts low the true output signal without removing the input signals. Typically, 4.6dB SD hysteresis is provided to prevent chattering. Signal Detect-Level Set A programmable, signal-detect level set pin sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and SDLVL sets the voltage at SDLVL. This voltage ranges from VCC to VREF. The external resistor creates a voltage divider between VCC and REF as shown in Figure 6. If desired, an appropriate external voltage may be applied rather than using a resistor. The relationship between VSDLVL and RSDLVL is given by:
RSDLVL RSDLVL + 2.8 where voltages are in volts and resistances are in k. The smaller the external resistor, which implies a smaller voltage difference from SDLVL to VCC, the lower the SD sensitivity. Hence, larger input amplitude is required to assert SD. The "Typical Operating Characteristics" section contains graphs showing the relationship between the input amplitude detection sensitivity and VSDLVL or RSDLVL. Hysteresis The SY88843V provides typically 4.6dB SD electrical hysteresis. By definition, a power ratio measured in dB is 10log(power ratio). Power is calculated as V2IN/R for an electrical signal. Hence, the same ratio can be stated as 20log(voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power and the ratios change linearly. Therefore, the optical hysteresis in dB is half the electrical hysteresis in dB given in the datasheet. The SY88843V provides typically 2.3dB SD optical hysteresis. As the SY88843V is an electrical device, this datasheet refers to hysteresis in electrical terms. With 4.6dB SD hysteresis, a voltage factor of 1.7 is required to assert SD. Hysteresis and Sensitivity Improvement If increased SD sensitivity and hysteresis are required, an application note entitled "Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers" is available at http:// www.micrel.com/product-info/app_hints+notes.shtml. VSDLVL = VCC - 1.3
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SY88843V
DATA+
5mV (Min.) VIS(mV) 900mV (Max.)
DATA-
(DATA+) - (DATA-)
10mVpp (Min.) VID(mVpp) 1800mVpp (Max.)
Figure 1. VIS and VID Definition
VCC 0.1F
VCC VCC
REF VCC
50 50 50 0.1F DOUT Z0 = 50 /DOUT 50
50 0.1F DIN 0.1F /DIN AC-Coupling Capacitors
50
Z0 = 50
AC-Coupling Capacitors
16mA
ESD STRUCTURE
ESD STRUCTURE
GND
GND
Figure 2. Input Structure
VCC
Figure 3. Output Structure
VCC
ICC
16mA
4.75k SD
50
50
Figure 5. SD Output Structure
ESD STRUCTURE
VCC
RSDLVL 16mA
SDLVL 2.8k
GND
REF
Figure 4. Power Supply Current Measurement
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Figure 6. SDLVL Setting Circuit
8
Micrel, Inc.
SY88843V
TYPICAL APPLICATIONS CIRCUIT
VCC
SD
0.1F
EN
0.1F
DOUT
From Transimpedance Amp.
0.1F
DIN /DIN
SY88843V
SDLVL REF
/DOUT
To CDR
0.1F
GND
VCC
100k
0.1F
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY88773V SY88823V SY88843V SY88973V Application Notes Function 3.3V/5V 3.2Gbps CML Low-Power, Limiting Post Amplifier w/ TTL LOS 3.3V/5V 3.2Gbps CML Low-Power, Limiting Post Amplifier w/ TTL SD 3.3V/5V 3.2Gbps CML Low-Power, Limiting Post Amplifier w/ TTL SD 3.3V/5V 3.2Gbps CML Low-Power, Limiting Post Amplifier w/ TTL LOS Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers Data Sheet Link http://www.micrel.com/_PDF/HBW/sy88773v.pdf http://www.micrel.com/_PDF/HBW/sy88823v.pdf http://www.micrel.com/_PDF/HBW/sy88843v.pdf http://www.micrel.com/_PDF/HBW/sy88973v.pdf http://www.micrel.com/product-info/app_hints+notes.shtml
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Micrel, Inc.
SY88843V
10 LEAD EPAD-MSOP (K10-2)
+0.08 -0.08 +0.003 -0.003 +0.05 -0.05 +0.002 -0.002
+0.15 -0.15 +0.004 -0.004
+0.10 -0.10 +0.004 -0.004
+0.008 -0.008 +0.003 -0.003
+0.07 -0.08 +0.003 -0.003
+0.15 -0.15 +0.006 -0.006
Rev.01
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Micrel, Inc.
SY88843V
16-PIN MicroLEADFRAMETM (MLF-16)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLFTM Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-110905 hbwhelp@micrel.com or (408) 955-1690
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